1. Field of the Invention
The present invention is related to a semiconductor integrated circuit, and in particular, relates to a technique to control an influence due to a process variation, that become remarkable in micro fabrication, generated at random between plural MOSFETs.
2. Description of the Related Art
In recent years, based on advancement of a micro process to the fabrication of a semiconductor integrated circuit device, the semiconductor integrated circuit device has been fabricated in the process where the channel-length of MOSFET is below 0.1-micron order. Along with such miniaturisation in the process, the characteristic variation based on an environmental temperature and the process variation becomes remarkable. On the other hand, the following reports are performed with respect to the above situation.
That is, as a technique that controls the above-mentioned characteristic variation, there is a method of constantly controlling an electric current between a source and a drain of the MOSFET of a P-type and an N-type by the substrate voltage as shown in a Japanese publication patent document (Japanese Patent Application Laid-open No. 2004-165649). According to this variation inhibition technique, the drain current of the MOSFET (in particular, the drain current in an arbitrary gate voltage value of a sub-threshold region or a saturation region) can be controlled so that there are neither a temperature dependency nor a process variation dependency, and the improvement of an operational stability can be achieved.
However, in the semiconductor manufacturing technique, although the process variation (Hereafter, it is called “random variation”) generated at random between the plural MOSFETs becomes remarkable along with miniaturisation, it is difficult to control the characteristic variation depending on such a random variation according to the above-mentioned conventional technique for controlling the variation. For example, in the path to decide an operation frequency, a delay time grows due to the random variation, and a setup error is occurred. Moreover, in the path where the holding restriction of flip-flop is severe, the delay time decreases by the random variation, and a holding error is occurred. For this case, it is impossible to avoid both errors at the same time according to the above-mentioned conventional technique for controlling the variation.